Thin film transistor and method for fabricating the same, display device, exposure device

ABSTRACT

A thin film transistor, a method for fabricating the same, a display device, and an exposure device are disclosed. The method comprises: patterning a source and drain layer by using a single slit mask and an exposure machine, to form a source, a drain, and an active region of the thin film transistor; wherein a pattern resolution of the single slit mask is not larger than a resolution of the exposure machine to form a groove shaped exposure pattern, wherein the groove shaped exposure pattern corresponds to the active region.

RELATED APPLICATIONS

The present application claims the benefit of Chinese Patent ApplicationNo. 201710512269.1, filed on Jun. 28, 2017, the entire disclosure ofwhich is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of thin film transistors,and particularly to a thin film transistor, a method for fabricating thesame, a display device, and an exposure device.

BACKGROUND

The characteristics of a thin film transistor (TFT) play a key role on acharging rate of a display device. Endeavors have been made tominiaturization of the TFT and improvement in its On-state current (Ion)in the art. A small size display device generally requires a low powerconsumption and high transmittance, which imminently requires reduce thesize of TFT by developing new narrow channel techniques. The oxide thinfilm transistor (Oxide TFT) technology is not mature yet, and the lowtemperature poly-silicon thin film transistor (LTPS TFT) is costly sothat it can not be applied to a production line of a high generation.Currently, amorphous silicon (a-Si) is used in an active layer of TFT inmost display device. TFTs resulting from this method comprise an activeregion which has a length generally larger than 3.5 μm. The activeregion indicates a channel region for carriers, which is formed on asurface region of the active layer between a source and a drain of theTFT during operation. As a result, the channel region has a largelength, and has a poor process stability which is strongly dependent onfabricating apparatuses.

SUMMARY

In a first aspect, it is provided a method for fabricating a thin filmtransistor, comprising: patterning a source and drain layer by using asingle slit mask (SSM) and an exposure machine, to form a source, adrain, and an active region of the thin film transistor; wherein apattern resolution of the single slit mask is not larger than aresolution of the exposure machine to form a groove shaped exposurepattern, wherein the groove shaped exposure pattern corresponds to theactive region.

In an exemplary embodiment, the step of patterning the source and drainlayer by using the single slit mask and the exposure machine, to formthe source, the drain, and the active region of the thin film transistorcomprises: coating a first photoresist on the source and drain layer;exposing and developing the first photoresist by using the single slitmask and the exposure machine according to a size of the source and thedrain, so that the resulting first photoresist on the source and drainlayer forms a groove shaped exposure pattern; ashing the firstphotoresist at a bottom of the groove shaped exposure pattern, to revealthe source and drain layer; wet etching the source and drain layer toform the source and the drain, and to reveal an active layer at aposition to which the groove shaped exposure pattern corresponds to formthe active region of the thin film transistor; and removing theremaining first photoresist.

In an exemplary embodiment, the ashing is performed for a duration ofabout 25˜100 seconds.

In an exemplary embodiment, the ashing is performed at a temperature ofabout 25˜60° C.

In an exemplary embodiment, an acid etching solution is used for wetetching the source and drain layer.

In an exemplary embodiment, prior to patterning the source and drainlayer by using the single slit mask and the exposure machine, the methodfurther comprises: forming an active layer on a substrate; forming asource and drain layer on the substrate and the active layer; whereinedges of an orthographic projection of the active layer on the substrateare aligned with edges of an orthographic projection of the source andthe drain of the thin film transistor.

In an exemplary embodiment, forming the active layer on the substratecomprises: forming an amorphous silicon layer on the substrate; coatinga second photoresist on the amorphous silicon layer; exposing anddeveloping the second photoresist by using a mask; etching the amorphoussilicon layer to form the active layer; and removing the remainingsecond photoresist.

In an exemplary embodiment, prior to patterning the source and drainlayer by using the single slit mask and the exposure machine, the methodfurther comprises: forming an active layer on a substrate; formingtransition layer on the active layer; and forming the source and drainlayer on the substrate and the transition layer, wherein edges of anorthographic projection of the active layer on the substrate are alignedwith edges of an orthographic projection of the source and the drain ofthe thin film transistor.

In an exemplary embodiment, the step of wet etching the source and drainlayer to form the source and the drain, and to reveal an active layer ata position to which the groove shaped exposure pattern corresponds toform the active region of the thin film transistor comprises: wetetching the source and drain layer to form the source and the drain, andto reveal the transition layer at a position to which the groove shapedexposure pattern corresponds; and dry etching the transition layer, toreveal the active layer to form the active region of the thin filmtransistor.

In an exemplary embodiment, the transition layer comprises phosphordoped amorphous silicon.

In an exemplary embodiment, the phosphor doped amorphous silicon isformed by using PH₃ and SiH₄ with a volume ratio about 2:1˜3:1.

In an exemplary embodiment, a duration for dry etching the transitionlayer is about 15˜30 seconds.

In a second aspect, it is provided a thin film transistor, wherein thethin film transistor comprises a active region which has a length notlarger than 3.5 μm.

In an exemplary embodiment, edges of an orthographic projection of theactive layer on the substrate are aligned with edges of an orthographicprojection of the source and the drain of the thin film transistor.

In a third aspect, it is provided a display device, comprising the thinfilm transistor as described above.

In a fourth aspect, it is provided an exposure device, comprising anexposure machine and a single slit mask, wherein a pattern resolution ofthe single slit mask is not larger than a resolution of the exposuremachine.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to explain the technical solutions in the embodiments of thepresent disclosure or the prior art more clearly, the drawings to beused in the description of the embodiments or the prior art will beintroduced briefly in the following, apparently, the drawings describedbelow are only some embodiments of the present disclosure, the ordinaryskilled person in the art, on the premise of not paying any creativework, can also obtain other drawings from these drawings.

FIG. 1 is a flow chart for illustrating a method for fabricating a thinfilm transistor in an embodiment of the present disclosure;

FIGS. 2a, 2b, 2c and 2d are structural views for illustrating a thinfilm transistor at different fabricating stages in an embodiment of thepresent disclosure;

FIG. 3 is a flow chart for illustrating a method for fabricating a thinfilm transistor in an embodiment of the present disclosure;

FIGS. 4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h, and 4i are structural views forillustrating a thin film transistor at different fabricating stages inan embodiment of the present disclosure;

FIG. 5 is a flow chart for illustrating steps for forming an activelayer in an embodiment of the present disclosure;

FIG. 6 is a flow chart for illustrating a method for fabricating a thinfilm transistor in an embodiment of the present disclosure;

FIGS. 7a, 7b, 7c, 7d, 7e, 7f, 7g, 7h, 7i, 7j, 7k are structural viewsfor illustrating a thin film transistor at different fabricating stagesin an embodiment of the present disclosure; and

FIG. 8 is a flow chart for illustrating steps for forming a source, adrain and an active region of a thin film transistor in an embodiment ofthe present disclosure.

DETAILED DESCRIPTION OF EMBODIMENTS

To make the objects, the technical solutions and the advantages ofembodiments of the present disclosure more apparent, the technicalsolutions of the embodiments of the present disclosure will be describedin detail hereinafter in conjunction with the drawings of theembodiments of the present disclosure. Apparently, the embodimentsdescribed hereinafter are only some embodiments of the presentdisclosure, but not all embodiments. Based the embodiments describedhereinafter, other embodiments obtained by those skilled in the artshould fall within the scope of the present disclosure.

Embodiments of the present disclosure provide a thin film transistor, amethod for fabricating the same, a display device, and an exposuredevice, to solve the problem in which a thin film transistor with anarrow channel region is difficult to fabricate.

An embodiment of the present disclosure provides a method forfabricating a thin film transistor. The method comprises: patterning asource and drain layer by using a single slit mask and an exposuremachine, to form a source, a drain, and an active region of the thinfilm transistor.

A pattern resolution of the single slit mask is not larger than aresolution of the exposure machine to form a groove shaped exposurepattern. The groove shaped exposure pattern corresponds to the activeregion. For example, the pattern resolution of the single slit mask canbe smaller than the resolution of the exposure machine by 2 μm. Thus,the resulting active region (i.e., channel region) is short, with alength not larger than 3.5 μm. This can improve the On-state current andcharging rate, and reduce the size of the thin film transistor.

As shown in FIG. 1 and FIGS. 2a-2d , the method comprises the followingsteps.

Step S101: coating a first photoresist 206 on a source and drain layer205.

This step is conducted at room temperature and atmospheric pressure.After coating, the first photoresist 206 needs baking.

It is noted that, prior to this step, a gate 202, an insulating layer203, an active layer 204 and the source and drain layer 205 have beenformed on a substrate 201 which are stacked in this order.

Step S102: exposing and developing the first photoresist 206 by using asingle slit mask and an exposure machine according to a predefined sizeof the source and the drain 208, so that the resulting first photoresist206 on the source and drain layer 205 forms a groove shaped exposurepattern 207.

As shown in FIG. 2a , in this step, the resulting first photoresist 206on the source and drain layer 205 forms the groove shaped exposurepattern 207 due to under exposure. The groove shaped exposure pattern207 generally reduces its width from an opening to a bottom, and forexample has a U shaped cross-section. During development with adeveloping solution, only the first photoresist 206 at the bottom of thegroove shaped exposure pattern 207 can be removed. This facilitatesforming subsequently an active region 209 with a small length.

Step S103: ashing the first photoresist 206 at the bottom of the grooveshaped exposure pattern 207, to reveal the source and drain layer 205.

The purpose of ashing is to consume the first photoresist 206 by anoxidation reaction, so as to thin the first photoresist 206.

The ashing adopts vapor phase ashing. The ashing gases comprises: SF₆,O₂ and He. In particular, the volume ratio of SF₆, O₂ and He is0.5˜2:30:0.5˜2. For example, the volume ratio of SF₆, O₂ and He is1:30:1. The pressure of ashing gases is 50 mT˜200 mT. For example, thepressure of ashing gases is 100 mT.

The temperature for ashing is about 25˜60° C. The duration for ashing isabout 25˜100 seconds. For example, the duration for ashing is 50seconds. By controlling the duration for ashing, the thickness of thefirst photoresist 206 which is reduced can be controlled, and thus theof the subsequently formed active region 209 can be controlled.

As shown in FIG. 2b , by this step, the first photoresist 206 at thebottom of the groove shaped exposure pattern 207 is removed, and thesource and drain layer 205 at the corresponding position is revealed.This facilitates subsequently etching the source and drain layer 205 atthis position.

Step S104: wet etching the source and drain layer 205 to form the sourceand the drain 208, and to reveal the active layer 204 at a position towhich the groove shaped exposure pattern 207 correspond to form theactive region 209 of the thin film transistor.

In the wet etching, the etching solution is acid etching solution. Theeffective component in the acid etching solution comprises cations likeH⁺, and anions like PO₄ ³⁻, Cl⁻, F⁻, NO₃ ⁻. The acid etching solution isformed by mixing a H₃PO₄ etching solution with other acid etchingsolutions in a molar concentration ratio of 7:1.

As shown in FIG. 2c , the first photoresist 206 acts as a blockinglayer, so that a portion of the source and drain layer 205 which doesnot contact the acid etching solution is retained. By patterning throughwet etching, this portion of the source and drain layer 205 forms thesource and the drain 208. The remaining portion of the source and drainlayer 205 is removed to reveal the active layer 204, and the activeregion 209 is formed between the source and the drain 208. Since the wetetching is conducted only once (for one time), this will not result in alarge critical dimension bias (CD bias). For example, the active region209 has a length smaller than a sum of the resolution size of theexposure machine and the CD bias of wet etching, i.e. not larger than3.5 μm.

Step S105: removing the remaining first photoresist 206.

As shown in FIG. 2d , after the remaining first photoresist 206 isremoved, the fabrication of thin film transistor is complete. The thinfilm transistor comprises the substrate 201, the gate 202, theinsulating layer 203, the active layer 204, the source and the drain 208which are stacked in this order. The active region 209 lies between thesource and the drain 208.

The source and the drain 208 and the active region 209 are formed by theprocess as described above.

In short, embodiments of the present disclosure provide a method forfabricating a thin film transistor. A mask which has a patternresolution not larger than a resolution of the exposure machine is used,and the active region 209 with a length not larger than 3.5 μm can beformed. This can improve the On-state current and the charging rate, andreduce the size of the thin film transistor.

Embodiments of the present disclosure provide a method for fabricating athin film transistor. In this embodiment, the active layer is formedseparately from the source and the drain. As shown in FIG. 3 and FIGS.4a-4i , the method comprises the following steps.

Step S31: forming the active layer 204 on the substrate 201.

Step S32: forming the source and drain layer 205 on the substrate 201and the active layer 204.

Step S33: patterning the source and drain layer 205 by using a singleslit mask and an exposure machine, to form the source and the drain 208and the active region 209 of thin film transistor.

Step S33 is identical with the step of forming the source and the drain208 and the active region 209 of the thin film transistor in theembodiment discussed with reference to FIG. 1 and FIGS. 2a-2d . Namely,a single slit mask with a pattern resolution not larger than aresolution of the exposure machine is used to form the groove shapedexposure pattern 207. A region of the source and drain layer 205 towhich the groove shaped exposure pattern 207 corresponds forms theactive region 209.

Thus, by applying the method as described above, the resulting thin filmtransistor comprises the active region 209 with a small length, which issimilar with the thin film transistor in the embodiment of FIG. 1 andFIGS. 2a-2d . Thus, the same beneficial effects as the embodiment ofFIG. 1 and FIGS. 2a-2d are obtained. In addition, in the fabricatingmethod of FIG. 3 and FIGS. 4a-4i , the active layer 204 and the sourceand the drain 208 are formed separately. Namely, the active layer 204and the source and the drain 208 are exposed and etched separately, sothat the processes for them will not interference with one another.Edges of an orthographic projection of the active layer 204 on thesubstrate 201 are aligned with edges of an orthographic projection ofthe source and the drain 208 on the substrate 201, so that there is noresidual of the active layer 204.

In particular, as shown in FIGS. 4a-4i and FIG. 5, step S31 comprisesthe followings steps.

Step S311: forming an amorphous silicon layer 210 on the substrate 201.

In particular, as shown in FIG. 4a , the amorphous silicon layer 210 canbe deposited by plasma enhanced chemical vapor deposition (PECVD). SiH₄,NH₃ and N₂ are used as the precursor gases. They are mixed at a certainvolume ratio, and react at temperature of about 300° C.˜400° C. and apower of about 1˜4 kW (e.g., 2 kW), to form the amorphous silicon layer210 on the substrate 201. For example, the volume ratio of SiH₄, NH₃ andN₂ is 1:5:16. During deposition, the duration of deposition can becontrolled to obtain the required thickness of the amorphous siliconlayer 210.

Step S312: coating a second photoresist 211 on the amorphous siliconlayer 210.

As shown in FIG. 4b , this step is conducted at a room temperature andan atmospheric pressure. After coating, the second photoresist 211 needsbaking.

Step S313: exposing and developing the second photoresist 211 with amask according to a predefined size of the active layer 204.

This step is conducted at a room temperature and an atmosphericpressure. As shown in FIG. 4b , in this step, the second photoresist 211is exposed and developed in certain regions according to the predefinedsize of the active layer 204.

Step S314: etching the amorphous silicon layer 210 to form the activelayer 204.

The etching can adopt dry etching, such as ICP (Inductively CoupledPlasma) and ECCP (Enhance Cathode Couple Plasma). In this step, SF₆ andCl₂ of a certain volume ratio are used as the reaction gases, and dryetching is conducted at a room temperature and a low vacuum environment.In particular, the volume ratio of SF₆ and Cl₂ can be about 0.5˜2:8,e.g., 1:8. The duration for etching can be selected according to therequired thickness of the active layer 204. Generally, the etchingduration for the active layer 204 with a thickness of 200 nm is about45˜60 seconds.

As shown in FIG. 4c , in this step, the amorphous silicon layer 210 ispatterned to form the active layer 204.

Step S315: removing the remaining second photoresist 211.

As shown in FIG. 4d , in particular, an organic solvent can be used todissolve the second photoresist 211 in a wet way. Also, vapor phasereaction (for example UN-ozone) can be applied to etch the secondphotoresist 211 in a dry way, so as to remove the second photoresist211.

The active layer 204 can be completed with the above steps.

In particular, as shown in FIG. 4e , the source and drain layer 205 isformed by sputtering or other methods for forming metallic films in stepS32. An orthographic projection of the active layer 204 on the substrate201 falls within an orthographic projection of the source and drainlayer 205 on the substrate 201.

In particular, as shown in FIG. 4f ˜FIG. 4i , step S33 is completelyidentical with steps for forming the source, the drain and the activeregion as shown in FIG. 1 and FIGS. 2a-2d , which is not repeated herefor simplicity.

In short, in the method for fabricating a thin film transistor shown inFIG. 3 and FIGS. 4a-4i , the mask with the pattern resolution not largerthan the resolution of the exposure machine is adopted. The activeregion 209 with a length not larger than 3.5 μm can be formed. This canimprove the On-state current and charging rate, and reduce the size ofthe thin film transistor. In addition, edges of an orthographicprojection of the active layer 204 on the substrate 201 are aligned withedges of an orthographic projection of the source and the drain 208 onthe substrate 201, so that there is no residual of the active layer 204.This can significantly reduce load and increase charging rate. Further,this can reduce a line width of the gate 202 and the source and thedrain 208, and increase aperture ratio.

An embodiment of the present disclosure provides a method forfabricating a thin film transistor. The present embodiment differs fromthe method of FIG. 3 and FIGS. 4a-4i in that, the present embodimentfurther comprises a step of forming a transition layer. As shown in FIG.6 and FIGS. 7a-7k , the fabricating method comprises the followingsteps.

Step S61: forming the active layer 204 on the substrate 201.

As shown in FIG. 7a ˜FIG. 7d , this step is identical with step S31 inFIG. 3 and FIGS. 4a-4i , which is not repeated here for simplicity.

Step S62: forming a transition layer 212 on the active layer 204.

This step is shown in FIG. 7e . The transition layer 212 comprisesphosphor doped amorphous silicon. PH₃ and SiH₄ with a volume ratio about2:13:1 are used to form the phosphor doped amorphous silicon. Thetransition layer 212 functions to increase the electrical conductivity.

Step S63: forming the source and drain layer 205 on the substrate 201and the transition layer 212.

As shown in FIG. 7f , this step is identical with step S32 in FIG. 3 andFIGS. 4a-4i , which is not repeated here for simplicity. The differencelies in that the source and drain layer 205 are formed on the substrate201 and the transition layer 212.

Step S64: patterning the source and drain layer 205 by using a singleslit mask and an exposure machine, to form the source and the drain 208and the active region 209 of the thin film transistor.

In step S62, the transition layer 212 is additionally formed. Thus, asshown in FIG. 8 and FIG. 7g ˜FIG. 7k , step S64 specifically comprisesthe following steps.

Step S641: coating the first photoresist 206 on the source and drainlayer 205.

Step S642: according to a predefined size of the source and the drain208, exposing and developing the first photoresist 206 by using a singleslit mask and an exposure machine, so that the resulting firstphotoresist 206 on the source and drain layer 205 forms the grooveshaped exposure pattern 207.

Step S643: ashing the first photoresist 206 at the bottom of the grooveshaped exposure pattern 207 to reveal the source and drain layer 205.

Step S644: wet etching the source and drain layer 205 to form the sourceand the drain 208, and to reveal the transition layer 212 at a positionto which the groove shaped exposure pattern 207 corresponds.

As shown in FIG. 7i , in this step, the transition layer 212 is revealedat a position to which the groove shaped exposure pattern 207corresponds.

Step S645: dry etching the transition layer 212 to reveal the activelayer 204, to form the active region 209 of the thin film transistor.

As shown in FIG. 7j , in this step, the active layer 204 is revealed.

The dry etching method can be ICP or ECCP. The duration for dry etchingthe transition layer 212 is about 15˜30 seconds. By controlling theduration for dry etching the transition layer 212, it is possible toprevent the active layer 204 from being etched.

The gases for dry etching the transition layer 212 comprise SF₆ and Cl₂,and dry etching is conducted at a room temperature and a low vacuumenvironment. In particular, the volume ratio of SF₆ and Cl₂ is about0.5˜2:8, e.g., 1:8.

Step S646: removing the remaining first photoresist 206.

In the above steps S641˜S646, other processes than the process of dryetching the transition layer 212 comprise the same parameters as stepS33 in FIG. 3 and FIGS. 4a-4i , which are not repeated here forsimplicity.

With the above steps, the source and the drain 208 and the active region209 are formed.

In short, in the method for fabricating a thin film transistor of thepresent embodiment, the mask with the pattern resolution not larger thanthe resolution of the exposure machine is adopted. The active region 209with a length not larger than 3.5 μm can be formed. This can improve theOn-state current and charging rate, and reduce the size of the thin filmtransistor. In addition, edges of an orthographic projection of theactive layer 204 on the substrate 201 are aligned with edges of anorthographic projection of the source and the drain 208 on the substrate201, so that there is no residual of the active layer 204. This cansignificantly reduce load and increase charging rate. Further, this canreduce a line width of the gate 202 and the source and the drain 208,and increase aperture ratio.

An embodiment of the present disclosure provides a thin film transistor.The thin film transistor is formed by the method described in theembodiment of FIG. 1 and FIGS. 2a-2d , the embodiment of FIG. 3 andFIGS. 4a-4i , or the embodiment of FIG. 6 and FIG. 7a -7 k.

As shown in FIG. 2d, 4i or 7 k, in the thin film transistor, the activeregion 209 has a length not larger than 3.5 μm. Thus, the active region209 of the thin film transistor is narrow.

For example, edges of an orthographic projection of the active layer 204on the substrate 201 are aligned with edges of an orthographicprojection of the source and the drain 208 on the substrate 201. Thus,there is no residual of the active layer 204 in the thin filmtransistor.

In short, in the thin film transistor of the present embodiment, edgesof an orthographic projection of the active layer 204 on the substrate201 are aligned with edges of an orthographic projection of the sourceand the drain 208 on the substrate 201, so that there is no residual ofthe active layer 204. This can significantly reduce load, and increasecharging rate. Further, this can reduce the line width of the gate 202and the source and the drain 208, and increase the aperture ratio. Theactive region 209 has a length not larger than 3.5 μm, which can improvethe On-state current and charging rate, and reduce the size of the thinfilm transistor.

An embodiment of the present disclosure provides a display device. Thedisplay device comprises the thin film transistor as described in theabove embodiments.

The display device comprises the thin film transistor of the aboveembodiments. There is no residual of the active layer. This cansignificantly reduce load, and increase charging rate. Further, this canreduce the line width of the gate, source and drain, and increaseaperture ratio. The active region 209 has a length not larger than 3.5μm, which can improve the On-state current and charging rate, and reducethe overall size of the thin film transistor.

An embodiment of the present disclosure provides an exposure device. Inparticular, the exposure device comprises an exposure machine and asingle slit mask. The single slit mask has a pattern resolution which isnot larger than a resolution of the exposure machine.

The exposure device can be used to fabricate a thin film transistor witha narrow active region, so that the active region has a length notlarger than 3.5 μm. This can improve the On-state current and chargingrate, and reduce the size of the thin film transistor.

Apparently, the person with ordinary skill in the art can make variousmodifications and variations to the present disclosure without departingfrom the spirit and the scope of the present disclosure. In this way,provided that these modifications and variations of the presentdisclosure belong to the scopes of the claims of the present disclosureand the equivalent technologies thereof, the present disclosure alsointends to encompass these modifications and variations.

What is claimed is:
 1. A method for fabricating a thin film transistor,comprising: patterning a source and drain layer by using a single slitmask and an exposure machine, to form a source, a drain, and an activeregion of the thin film transistor; wherein a pattern resolution of thesingle slit mask is not larger than a resolution of the exposure machineto form a groove shaped exposure pattern, wherein the groove shapedexposure pattern corresponds to the active region.
 2. The method ofclaim 1, wherein the step of patterning the source and drain layer byusing the single slit mask and the exposure machine, to form the source,the drain, and the active region of the thin film transistor comprises:coating a first photoresist on the source and drain layer; exposing anddeveloping the first photoresist by using the single slit mask and theexposure machine according to a size of the source and the drain, sothat the resulting first photoresist on the source and drain layer formsa groove shaped exposure pattern; ashing the first photoresist at abottom of the groove shaped exposure pattern, to reveal the source anddrain layer; wet etching the source and drain layer to form the sourceand the drain, and to reveal an active layer at a position to which thegroove shaped exposure pattern corresponds to form the active region ofthe thin film transistor; and removing the remaining first photoresist.3. The method of claim 2, wherein the ashing is performed for a durationof about 25˜100 seconds.
 4. The method of claim 2, wherein the ashing isperformed at a temperature of about 25˜60° C.
 5. The method of claim 2,wherein an acid etching solution is used for wet etching the source anddrain layer.
 6. The method of claim 1, wherein prior to patterning thesource and drain layer by using the single slit mask and the exposuremachine, the method further comprises: forming an active layer on asubstrate; forming a source and drain layer on the substrate and theactive layer; wherein edges of an orthographic projection of the activelayer on the substrate are aligned with edges of an orthographicprojection of the source and the drain of the thin film transistor. 7.The method of claim 6, wherein forming the active layer on the substratecomprises: forming an amorphous silicon layer on the substrate; coatinga second photoresist on the amorphous silicon layer; exposing anddeveloping the second photoresist by using a mask; etching the amorphoussilicon layer to form the active layer; and removing the remainingsecond photoresist.
 8. The method of claim 2, wherein prior topatterning the source and drain layer by using the single slit mask andthe exposure machine, the method further comprises: forming an activelayer on a substrate; forming transition layer on the active layer; andforming the source and drain layer on the substrate and the transitionlayer, wherein edges of an orthographic projection of the active layeron the substrate are aligned with edges of an orthographic projection ofthe source and the drain of the thin film transistor.
 9. The method ofclaim 8, wherein the step of wet etching the source and drain layer toform the source and the drain, and to reveal an active layer at aposition to which the groove shaped exposure pattern corresponds to formthe active region of the thin film transistor comprises: wet etching thesource and drain layer to form the source and the drain, and to revealthe transition layer at a position to which the groove shaped exposurepattern corresponds; and dry etching the transition layer, to reveal theactive layer to form the active region of the thin film transistor. 10.The method of claim 9, wherein the transition layer comprises phosphordoped amorphous silicon.
 11. The method of claim 10, wherein thephosphor doped amorphous silicon is formed by using PH₃ and SiH₄ with avolume ratio about 2:1˜3:1.
 12. The method of claim 9, wherein aduration for dry etching the transition layer is about 15˜30 seconds.13. A thin film transistor, wherein the thin film transistor comprisesan active region which has a length not larger than 3.5 μm.
 14. The thinfilm transistor of claim 13, wherein edges of an orthographic projectionof the active layer on the substrate are aligned with edges of anorthographic projection of the source and the drain of the thin filmtransistor.
 15. A display device, comprising the thin film transistor ofclaim
 14. 16. An exposure device, comprising an exposure machine and asingle slit mask, wherein a pattern resolution of the single slit maskis not larger than a resolution of the exposure machine.